(1) Field of the Invention
The present invention relates to a bus arbitration system used between a plurality of devices for granting use of a bus having a data bus size larger than a port size of each of the plurality of devices.
(2) Description of the Related Art
Generally, in computer systems, a strong demand exists for increased capacity and speed of data transfer in a bus system.
In the prior art, speeding up of data transfer was carried out by, for example, (1) using a high-speed clock for controlling timing of operation, (2) increasing an amount of data transferred at one time, and (3) improving an efficiency of proccessing by eliminating idle time.
Generally, in a system wherein a plurality of devices are connected to a bus, when requests to use the bus are made by more than one of the devices at the same time, arbitration is carried out between the devices, to determine use of the bus, by a bus arbiter. In such a system, a device having requested use of the bus, but not yet granted use by the bus arbitration, must wait until any other device which has been granted use of the bus by the bus arbitration, is finished.
Generally, however, each device connected to a bus has an individual port size (number of data signal lines used for data input/output, i.e., number of bits of a data input/output port), for example, 8 bits, 16 bits, or 32 bits, and naturally the data bus size (number of data lines) in a bus is equal to or larger than the maximum port size of the devices connected to the bus.
In the prior art, the bus arbitration is carried out only for use of the whole data bus. Therefore, for example, in a system wherein a plurality of devices are connected to a bus having a data bus size of 32 bits, and devices have port sizes of 8 bits, 16 bits, and 32 bits, respectively, while one of the devices having a port size of 8 bits is using the bus, the other devices having port sizes of 8 bits, and 16 bits, and 32 bits, respectively, must wait until the device is through using the bus. Namely, during the use of the bus by the 8 bit device, since only 8 bits of the 32 bits bus are actually used, the other 24 bits of the bus are actually in an idle state. This means that in the prior art, the efficency of data transfer is very low when a plurality of devices are connected to a bus, each of the devices having a port size smaller than the bus size.